Product Summary

The MT46H64M16LFCK-6IT is a 1Gb Mobile low-power DDR SDRAM. It is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. The MT46H64M16LFCK-6IT is internally configured as a quad-bank DRAM. Each of the x16’s 268,435,456-bit banks is organized as 16,384 rows by 1,024 columns by 16 bits. Each of the x32’s 268,435,456-bit banks is organized as 8,192 rows by 1,024 columns by 32 bits. In the reduced page-size (LG) option, each of the x32’s 268,435,456-bit banks are organized as 16,384 rows by 512 columns by 32 bits.

Parametrics

MT46H64M16LFCK-6IT absolute maximum ratings: (1)VDD/VDDQ supply voltage relative to VSS: -1.0 to 2.4 V; (2)Voltage on any pin relative to VSS: -0.5 V to 2.4 V or (VDDQ + 0.3V), whichever is less; (3)Storage temperature (plastic): -55 to +150 ℃.

Features

MT46H64M16LFCK-6IT features: (1)VDD/VDDQ = 1.70-1.95V; (2)Bidirectional data strobe per byte of data (DQS); (3)Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle; (4)Differential clock inputs (CK and CK#); (5)Commands entered on each positive CK edge; (6)DQS edge-aligned with data for READs; centeraligned with data for WRITEs; (7)4 internal banks for concurrent operation; (8)Data masks (DM) for masking write data-one mask per byte; (9)Programmable burst lengths (BL): 2, 4, 8, or 161; (10)Concurrent auto precharge option is supported; (11)Auto refresh and self refresh modes; (12)1.8V LVCMOS-compatible inputs; (13)On-chip temp sensor to control self refresh rate; (14)Partial-array self refresh (PASR); (15)Deep power-down (DPD); (16)Status read register (SRR); (17)Selectable output drive strength (DS); (18)Clock stop capability; (19)64ms refresh.

Diagrams

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MT46H128M16LFCK-5 IT:A

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Other

Data Sheet
Negotiable