XC2C256-7FTG256C

CoolRunner-II CPLD, BGA, 1.8V

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Price:: US $5.30~9.50 / piece [Get Latest Price]

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	US $5.30~9.50

PartNumber:: XC2C256-7FTG256C

Brand:: Xilinx, Inc - Xilinx | Pack: BGA | D/C: 09+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-02-21

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Part Number:XC2C256-7FTG256C
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Product Summary

The XC2C256-7FTG256C is a 256-macrocell CoolRunner-II CPLD. It is designed for both high performance and low power applications. The XC2C256-7FTG256C consists of sixteen Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.

Parametrics

XC2C256-7FTG256C absolute maximum ratings: (1)Supply voltage relative to ground:–0.5V to 2.0 V; (2)Supply voltage for output drivers:–0.5V to 4.0 V; (3)JTAG input voltage limits:–0.5V to 4.0 V; (4)JTAG input supply voltage:–0.5V to 4.0 V; (5)Input voltage relative to ground:–0.5V to 4.0 V; (6)Voltage applied to 3-state output:–0.5V to 4.0 V; (7)Storage Temperature (ambient):–65℃ to +150℃; (8)Junction Temperature:+150℃.

Features

XC2C256-7FTG256C features: (1)Global signal options with macrocell control:Multiple global clocks with phase selection per macrocell,Multiple global output enables,Global set/reset; (2)Advanced design security; (3)PLA architecture:Superior pinout retention,100% product term routability across function block; (4)Open-drain output option for Wired-OR and LED drive; (5)Optional bus-hold, 3-state or weak pull-up on selected I/O pins; (6)Optional configurable grounds on unused I/Os; (7)Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels; (8)Fastest in system programming; (9)1.8V ISP using IEEE 1532 (JTAG) interface; (10)IEEE1149.1 JTAG Boundary Scan Test; (11)Optional Schmitt-trigger input (per pin); (12)Unsurpassed low power management; (13)DataGATE enable (DGE) signal control; (14)Two separate I/O banks; (15)RealDigital 100% CMOS product term generation; (16)Flexible clocking modes; (17)As fast as 5.7 ns pin-to-pin delays; (18)As low as 13 μA quiescent current .