CA91C142D-33IE

CMOS AccelArray, -0.5 VDDE + 0.5, structured ASIC, low development cost, 3 to 4 metal layers, 6 million logic gates

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Price:: US $77.00~92.00 / piece [Get Latest Price]

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	US $77.00~92.00

PartNumber:: CA91C142D-33IE

Brand:: Tundra Semiconductor Corporation - Tundra | Pack: BGA | D/C: 02+

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Products Upload time: 2012-02-20

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Product Summary

The CA91C142D-33IE is a new structured ASIC, offering short development time, and low development cost with pre-diffused IP macros into base masters and pre-designed common 3 to 4 metal layers out of 6 to 7 layers. By using 0.11 μm CMOS process technology, the CA91C142D-33IE can support 6 million logic gates, 4.55 Mbits SRAM and 3.125 Gbps high speed transmission macros. Ultra-high pin count FC-BGA (up to 729 pins to 1681 pins) packages of the CA91C142D-33IE are available.

Parametrics

CA91C142D-33IE absolute maximum ratings: (1)Operation junction temperature Tj: -40 to + 125 ℃; (2)Storage temperature Tst: -55 to + 125 ℃; (3)Output voltage VO: 2.5 V CMOS: -0.5 VDDE + 0.5 ( ≤ 3.6) V; (4)Input voltage VI 2.5 V CMOS: -0.5 VDDE + 0.5 ( ≤ 3.6) V; (5)Power supply voltage VDD: -0.5 to 3.6 V.

Features

CA91C142D-33IE features: (1)Uses an architecture that simplifies physical design tasks; (2)Pre-designed common masters with IR-drop free; (3)Pre-designed test circuit insertion to reduce test synthesis tasks.; (4)Uses a dedicated timing-driven layout tool to reduce development time; (5)Signal Integrity Free (pre-designed main clock trees without design verifications); (6)Max built-in gate number : 6,000,000 gates or more; (7)Technology : 0.11 μm Silicon gate CMOS, 6 to 7-metal layers (wiring material: copper), low-k inter-layer film; (8)Internal cells support high-speed operation; (9)Operation junction temperature : -40 ℃ to +125 ℃ (standard); (10)Max operating frequency: 333 MHz (internal circuit); (11)Support for fast interface/macro (200 MHz/400 MHz DDR I/F, 2.5 Gbps PCI Express, 3.125 Gbps XAUI, etc.); (12)Special interfaces (P-CML,LVDS,PCI,HSTL,SSTL-2, etc.); (13)Embedded macro : PLL, SRAM; (14)8-channel clock supply system incorporating a PLL; (15)Supports Memory-BIST/Boundary-SCAN; (16)Package : FC-BGA (729 pins to 1681 pins); (17)ARM core is supported.