EPM240T100C3N

Product Summary

The EPM240T100C3N is a non-volatile CPLD. The EPM240T100C3N is based on a 0.18-µm, 6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. It offers high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. The EPM240T100C3N is designed to reduce cost and power while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset (POR) and sequencing control, and device configuration control.

Parametrics

EPM240T100C3N absolute maximum ratings: (1)Internal supply voltage:–0.5V to 4.6V; (2)I/O supply voltage:–0.5V to 4.6V; (3)DC input voltage:–0.5V to 4.6V; (4)DC output current, per pin:–25mA to 25mA; (5)Storage temperature:–65℃ to 150℃; (6)Ambient temperature:–65℃ to 135℃; (7)Junction temperature:135℃.

Features

EPM240T100C3N features: (1)Low-cost, low-power CPLD ; (2)Instant-on, non-volatile architecture; (3)Standby current as low as 29 μA; (4)Provides fast propagation delay and clock-to-output times; (5)Provides four global clocks with two clocks available per logic array block (LAB); (6)UFM block up to 8 Kbits for non-volatile storage; (7)MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V; (8)MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels; (9)Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors; (10)Schmitt triggers enabling noise tolerant inputs (programmable per pin); (11)I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66MHz ; (12)Supports hot-socketing; (13)Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (14)ISP circuitry compliant with IEEE Std. 1532.

Diagrams