Product Summary

The EPM240T100C5 contains a two-dimensional row and column-based architecture to implement custom logic. Row and column interconnects provide signal interconnects between the logic array blocks (LABs). The logic array of EPM240T100C5 consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. The MultiTrack interconnect provides fast granular timing delays between LABs. The fast routing between LEs provides minimum timing delay for added levels of logic versus globally routed interconnect structures. The EPM240T100C5 I/O pins are fed by I/O elements (IOE) located at the ends of LAB rows and columns around the periphery of the device. Each IOE contains a bidirectional I/O buffer with several advanced features. I/O pins support Schmitt trigger inputs and various single-ended standards, such as 66-MHz, 32-bit PCI, and LVTTL.

Parametrics

EPM240T100C5 absolute maixmum ratings: (1)VCCINT Internal supply voltage With respect to ground: -0.5 to 4.6 V; (2)VCCIO I/O supply voltage: -0.5 to 4.6 V; (3)VI DC input voltage: -0.5 to 4.6 V; (4)IOUT DC output current, per pin: -25 25 mA; (5)TSTG Storage temperature No bias: –65 to 150 ℃; (6)TAMB Ambient temperature Under bias: –65 to 135℃; (7)TJ Junction temperature TQFP and BGA packages under bias: 135℃.

Features

EPM240T100C5 features: (1)Low-cost, low-power CPLD; (2)Instant-on, non-volatile architecture; (3)Standby current as low as 29 μA; (4)Provides fast propagation delay and clock-to-output times; (5)Provides four global clocks with two clocks available per logic array block (LAB); (6)UFM block up to 8 Kbits for non-volatile storage; (7)MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V; (8)MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels; (9)Bus-friendly architecture including programmable slew rate, drive strength, bushold, and programmable pull-up resistors; (10)Schmitt triggers enabling noise tolerant inputs (programmable per pin); (11)I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz; (12)Supports hot-socketing; (13)Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (14)ISP circuitry compliant with IEEE Std. 1532.

Diagrams

EPM240T100C5 block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
EPM240T100C5
EPM240T100C5


IC MAX II CPLD 240 LE 100-TQFP

Data Sheet

0-1: $3.96
EPM240T100C5N
EPM240T100C5N


IC MAX II CPLD 240 LE 100-TQFP

Data Sheet

0-1: $3.60