ADSP-21161NKCA-100

Product Summary

The ADSP-21161NKCA-100 is a DSP Microcomputer. It is source code compatible with the ADSP-21160 and with first generation ADSP-2106x SHARCs in SISD (Single Instruction, Single Data) mode. Like other SHARC DSPs, the ADSP-21161NKCA-100 is a 32-bit processor that is optimized for high performance DSP applications. The device includes a 100 MHz core, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks. The ADSP-21161NKCA-100 offers a Single-Instruction-Multiple-Data (SIMD) architecture. Using two computational units, the device can double cycle performance versus the ADSP-2106x on a range of DSP algorithms.

Parametrics

ADSP-21161NKCA-100 absolute maximum ratings: (1)Internal (Core) Supply Voltage (VDDINT): –0.3 V to +2.2 V; (2)Analog (PLL) Supply Voltage (AVDD): –0.3 V to +2.2 V; (3)External (I/O) Supply Voltage (VDDEXT): –0.3 V to +4.6 V; (4)Input Voltage: –0.5 V to VDDEXT + 0.5 V; (5)Output Voltage Swing: –0.5 V to VDDEXT + 0.5 V; (6)Load Capacitance: 200 pF; (7)Storage Temperature Range: –65 to +150℃.

Features

ADSP-21161NKCA-100 features: (1)100 MHz (10 ns) Core Instruction Rate; (2)Single-Cycle Instruction Execution, Including SIMD Operations in Both Computational Units; (3)600 MFLOPs Peak and 400 MFLOPs Sustained Performance; (4)225-Ball 17 mm × 17 mm MBGA Package; (5)200 Million Fixed-Point MACs Sustained Performance; (6)Dual Data Address Generators (DAGs) with Modulo and Bit-Reverse Addressing; (7)Zero-Overhead Looping with Single-Cycle Loop Setup, Providing Efficient Program Sequencing; (8)IEEE 1149.1 JTAG Standard Test Access Port and On-Chip Emulation; (9)64-Bit Background DMA Transfers at Core Clock Speed, in Parallel with Full-Speed Processor Execution; (10)800 M Bytes/s Transfer Rate over IOP Bus Host Processor Interface to 8-, 16-, and 32-Bit; (11)Microprocessors; the Host Can Directly Read/Write ADSP-21161N IOP Registers.

Diagrams