MC68EC030FE40C

Product Summary

The MC68EC030FE40C is a 32-bit embedded controller that streamlines the functionality of an MC68030 for the requirements of embedded control applications. The device is optimized to maintain performance while using cost-effective memory subsystems. The MC68EC030FE40C incorporates the capabilities of the MC68030 integer unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on one VLSI device. The MC68EC030FE40C maintains the 32-bit registers available with the entire M68000 Family as well as the 32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor interface provided with the MC68020 and MC68030.

Parametrics

MC68EC030FE40C absolute maximum ratings: (1)Supply Voltage:-0.3V to +7.0V; (2)Input Voltage:-0.5V to +7.0V; (3)Operating Temperature Range: Minimum Ambient Temperature:0℃, Maximum Ambient Temperature:70℃; (4)Storage Temperature Range:-55℃ to 150℃.

Features

MC68EC030FE40C features: (1)Burst-Mode Bus Interface for Efficient DRAM Access; (2)On-Chip Data Cache (256 Bytes) and On-Chip Instruction Cache(256 Byte); (3)Dynamic Bus Sizing for Direct Interface to 8-, 16-, and 32-Bit Devices; (4)25- and 40-MHz Operating Frequency (up to 9.2 MIPS); (5)Advanced Plastic Pin Grid Array Packaging for Through-Hole Applications; (6)Complete 32-Bit Nonmultiplexed Address and Data Buses; (7)Sixteen 32-Bit General-Purpose Data and Address Registers; (8)Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers; (9)Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection; (10)Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum), Synchronous Bus Cycle (two clocks minimum), and Burst Data Transfers (one clock); (11)Complete Support for Coprocessors with the M68000 Coprocessor Interface; (12)Internal Status Indication for Hardware Emulation Support; (13)4-Gbyte Direct Addressing Range; (14)Implemented in Motorola’s HCMOS Technology That Allows CMOS and HMOS (High-Density NMOS) Gates To Be Combined for Maximum Speed, Low Power, and Small Die Size.

Diagrams