Product Summary

The XC2C256-7VQ100C is a CPLD. The XC2C256-7VQ100C is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. The XC2C256-7VQ100C consists of sixteen Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.

Parametrics

XC2C256-7VQ100C absolute maximum ratings: (1)VCC, Supply voltage relative to ground: –0.5 to 2.0 V; (2)VCCIO, Supply voltage for output drivers: –0.5 to 4.0 V; (3)VJTAG, JTAG input voltage limits: –0.5 to 4.0 V; (4)VAUX, JTAG input supply voltage: –0.5 to 4.0 V; (5)VIN, Input voltage relative to ground: –0.5 to 4.0 V; (6)VTS, Voltage applied to 3-state output: –0.5 to 4.0 V; (7)TSTG, Storage Temperature (ambient): –65 to +150℃; (8)TJ, Junction Temperature: +150℃.

Features

XC2C256-7VQ100C features: (1)As fast as 5.7 ns pin-to-pin delays; (2)As low as 13 μA quiescent current; (3)Optimized architecture for effective logic synthesis; (4)Refer to the CoolRunner.-II family data sheet for architecture description; (5)Multi-voltage I/O operation: 1.5V to 3.3V; (6)Optional bus-hold, 3-state or weak pull-up on selected I/O pins; (7)Optional configurable grounds on unused I/Os; (8)Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels; (9)Two separate I/O banks; (10)RealDigital 100% CMOS product term generation.

Diagrams

XC2C128
XC2C128

Other


Data Sheet

Negotiable 
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